Hao Zheng, an associate professor in the , has secured a $599,493 grant from the National Science Foundation (NSF) for his groundbreaking research on improving System-on-Chip (SoC) designs. The project, 鈥淪HF: Small: A Communication-Centric Validation Framework for System-on-Chip Designs,鈥� aims to enhance the safety, reliability, and security of these critical hardware systems. Read more about the award .
About the Research
SoC designs power a diverse range of applications, from healthcare devices to industrial automation systems. However, their increasing complexity can introduce vulnerabilities and errors. Zheng鈥檚 research focuses on communication-centric approaches to improve and streamline SoC design validation throughout the entire development cycle, addressing key challenges in pre-silicon verification and post-silicon debugging. Additionally, the research leverages recent advances in deep sequence modeling to unify various aspects of SoC validation, resulting in a comprehensive framework that will significantly boost both the productivity and quality of SoC validation. This work will ultimately provide greater assurance in the deployed SoC designs.
鈥淰alidation typically accounts for about 70% of the total design cost in a System-on-Chip (SoC) project, making it the most resource-intensive phase of development. This research tackles some fundamental challenges in SoC validation, offering solutions that can dramatically improve efficiency and effectiveness of current validation practice,鈥� said Hao Zheng.
More About Professor Zheng
Hao Zheng received his Ph.D. from the Electrical and Computer Engineering department at the University of Utah in 2001. He joined the Computer Science and Engineering department at the 最新天美传媒 in 2004 where he is currently an Associate Professor. His general research interests are in computer architecture, electronic design automation, and hardware/software test and verification.
Recently, his main research focuses are on developing efficient approaches and techniques for system integration validation and debug of SoC designs, runtime monitoring mechanisms for SoC security, and specification mining using machine learning techniques. His other interests include formal methods for verifying embedded/cyber-physical system design. He received an NSF CAREER Award in 2006, a USF Outstanding Research Achievement Award in 2007, and a Best Paper Award in the International SPIN Symposium on Model Checking Software in 2014. He has been served in program committees of various conferences and is currently an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
The project promises to advance the field of verification and validation, foster industry collaboration, and provide valuable training opportunities for students at USF.
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